1. Technical Field
The present invention relates to a test apparatus and a circuit apparatus. More particularly, the present invention relates to a test apparatus designed to test a device under test and a circuit device for use in the test apparatus.
2. Related Art
Writing/reading operations are performed between a semiconductor test apparatus and a plurality of LSIs by means of a known bus interface scheme. For example, Patent Document 1 discloses a bus interface scheme that enables writing/reading operations to be performed between a CPU and a plurality of devices such as LSIs in a complex manner of selections.    Patent Document 1: Japanese Utility Model No. 3067794
According to the above-mentioned bus interface scheme, however, an increase in the number of devices results in an increase in the number of buses connecting the CPU and the devices to each other. Therefore, a large number of devices means a large number of buses, which leads to a large number of signals transmitted through the buses.